It's also possible to change its period, duty, logic values and first edge. One essential signal is, of course, the clock. So right click each signal > Add to > Wave > Selected Signals. In the Objects tab, choose every signal you would like to add to the simulation. To see your signals in simulation, let's add them into the famous wave. In the Processes there are all assign signals. In the Objects tab there are parameter, input, output, inout, wire, reg signals. In the Sim tab you could see every signals and blocks of your modules. Indeed, you could write it down directly a command line.Īt this point, three new tabs have opened: Note that this Transcript window could be see as a console. Inside the Transcript window you could see something like that: In the Design Units input you have now: badprog.hellosim. Open the badprog design (with a "+" before) > select hellosim.v. The Start Simulation window has appeared. Simulatingįrom ModelSim > Simulate > Start Simulation. If there were an error, a red cross will appear. If all was correct, you should have a green tick instead of the blue question mark. Right click hellosim.v and select > Compile Selected.
Modelsim altera starter edition code#
To see the file itself, double click it, the code will appear on the right. It means that the file hasn't been validated yet. > select the hellosim.v file from your own project > OK.Ī blue question mark has appeared in the Status column in front of your file. So let's import the hellosim.v file from our project.įrom ModelSim, in the Library window, there are, at bottom, two tabs.Ĭlick Project, then right click on the white pan to open a window menu > Add to Project > Existing File. Notice that if we had several files, we would have to import them all. Let's say this project is called HelloSim and the file inside is hellosim.v (yes it's a Verilog file, but any HDL will be correct). Oh, of course, you've to create a project in an HDL, such as Verilog for example. OK, now we've to import existing files into project.
It asks to write a project name, a project location and a default library name. Creating a new projectįrom the ModelSim window > File > New > Project. To open ModelSim-Altera Starter Edition, from Quartus > Tools > Run Simulation Tool > RTL Simulation. The timing simulation is checked only if the functional is correct.Īnother difference between functional and timing simulation is that the first is fast, the second is sure.īut to have a great design circuit both are necessary of course. In general, the functional simulation is made first. That's exactly as if you looked on a real device. The timing simulation is different because it adds a notion of time. That's how electrons could pass through the circuit. The functional simulation checks only if wires and gates seem correct in order to say if the circuit's design could be validated.Īctually it checks how the circuit behaves after applying inputs. There are two different types of simulation: You could use it with any HDL such as VHDL, Verilog or SystemVerilog. To be honest a simulation tool is really complex to handle, so this tutorial will be most an introduction than exhaustive examples. This is what we're going to see in this ModelSim-Altera Starter Edition introduction. After installing ModelSim-Altera Starter Edition, what's better than testing it?